US 12,266,728 B2
Semiconductor device and method of manufacture
Wan-Yi Kao, Baoshan Township (TW); Yu-Cheng Shiau, Hsinchu (TW); Chunyao Wang, Zhubei (TW); Chih-Tang Peng, Zhubei (TW); Yung-Cheng Lu, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 29, 2024, as Appl. No. 18/591,730.
Application 18/591,730 is a continuation of application No. 18/064,562, filed on Dec. 12, 2022, granted, now 11,942,549.
Application 18/064,562 is a continuation of application No. 17/157,330, filed on Jan. 25, 2021, granted, now 11,527,653, issued on Dec. 13, 2022.
Claims priority of provisional application 63/055,045, filed on Jul. 22, 2020.
Prior Publication US 2024/0204104 A1, Jun. 20, 2024
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 21/0214 (2013.01); H01L 21/02211 (2013.01); H01L 21/02263 (2013.01); H01L 21/76224 (2013.01); H01L 21/76232 (2013.01); H01L 21/823481 (2013.01); H01L 27/0924 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 21/76227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first liner extending between a first semiconductor fin and a second semiconductor fin over a semiconductor substrate;
a second liner in physical contact with the first liner;
a third liner in physical contact with the second liner, the third liner comprising nitrogen at a percentage of less than about 10%;
a fourth liner in physical contact with the third liner;
a capping layer in physical contact with the fourth liner, the capping layer comprising carbon at a percentage of less than about 10%;
a dielectric cap in physical contact with the capping layer, wherein the first semiconductor fin extends further away from the semiconductor substrate than the dielectric cap; and
a dielectric fin embedded within the dielectric cap and extending further away from the semiconductor substrate than the dielectric cap.