US 12,266,726 B2
Shielded gate trench MOSFETs with improved performance structures
Fu-Yuan Hsieh, New Taipei (TW)
Assigned to NAMI MOS CO., LTD., New Taipei (TW)
Filed by Nami MOS CO., LTD., New Taipei (TW)
Filed on Apr. 7, 2022, as Appl. No. 17/715,089.
Prior Publication US 2023/0327013 A1, Oct. 12, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01)
CPC H01L 29/7813 (2013.01) [H01L 29/063 (2013.01); H01L 29/0638 (2013.01); H01L 29/1095 (2013.01); H01L 29/407 (2013.01); H01L 29/408 (2013.01); H01L 29/7811 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shielded gate trench (SGT) MOSFET formed in an epitaxial layer of a first conductivity type onto a substrate of said first conductivity type, comprising:
a plurality of gate trenches formed in an active area, surrounded by source regions of said first conductivity type are encompassed in body regions of a second conductivity type near a top surface of said epitaxial layer, each of said plurality of gate trenches is filled with a gate electrode and a shielded gate electrode; said shielded gate electrode is insulated from said epitaxial layer by a first insulating film, said gate electrode is insulated from said epitaxial layer by a gate oxide, said shielded gate electrode and said gate electrode are insulated from each other by an Inter-Poly Oxide (IPO) film, said gate oxide surrounds said gate electrode and has less thickness than said first insulating film;
an Oxide Charge Balance (OCB) region formed between two adjacent of said plurality of gate trenches below said body regions and above a bottom of said shielded gate electrode;
a buffer region formed between said substrate and said OCB region;
said body regions, said shielded gate electrode and said source regions are shorted together to a source metal through a plurality of trench contacts;
said epitaxial layer in said OCB region has multiple stepped epitaxial (MSE) layers with different doping concentrations decreasing stepwise in a direction from a bottom of said shielded gate electrode to said body regions along sidewalls of said plurality of gate trenches, wherein each of said multiple stepped-epitaxial layers has a uniform doping concentration as grown;
said SGT MOSFET further comprising an edge termination area having multiple edge trenches; a trench field plate is disposed in each of said multiple edge trenches and insulated from said epitaxial layer by a second insulating film, wherein said each of said multiple edge trenches has a trench width and a trench depth greater than or equal to said each of said plurality of gate trenches in the said active area; and
an electric field reducing region of said first conductivity type surrounding each bottom of said plurality of gate trenches in said active area and of said multiple edge trenches in said edge termination area with a doping concentration lower than said epitaxial layer in said buffer region.