US 12,266,725 B2
Lateral III-nitride devices including a vertical gate module
Umesh Mishra, Montecito, CA (US); Davide Bisi, Goleta, CA (US); Geetak Gupta, Goleta, CA (US); Carl Joseph Neufeld, Goleta, CA (US); Brian L. Swenson, Santa Barbara, CA (US); and Rakesh K. Lal, Isla Vista, CA (US)
Assigned to Transphorm Technology, Inc., Goleta, CA (US)
Filed by Transphorm Technology, Inc., Goleta, CA (US)
Filed on Jul. 8, 2020, as Appl. No. 16/923,587.
Application 16/923,587 is a division of application No. 16/598,510, filed on Oct. 10, 2019, granted, now 10,756,207.
Claims priority of provisional application 62/745,213, filed on Oct. 12, 2018.
Prior Publication US 2020/0343375 A1, Oct. 29, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/778 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7788 (2013.01) [H01L 29/0692 (2013.01); H01L 29/1037 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/7783 (2013.01); H01L 29/2003 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A III-N device, comprising:
a III-N material structure comprising a III-N channel layer over a III-N barrier layer, a p-type III-N layer over and directly contacting the III-N channel layer, and a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer;
an n-type III-N layer over and directly contacting the p-type III-N layer,
a source electrode, a gate electrode, and a drain electrode each on a same side of the III-N material structure;
a gate insulator layer separating the gate electrode from the p-type III-N layer and the III-N channel layer; wherein
the source electrode directly contacts the n-type III-N layer and is electrically connected to the p-type III-N layer;
the drain electrode is electrically connected to the 2DEG channel;
a portion of the III-N channel layer separates the gate insulator layer from the III-N barrier layer;
the p-type III-N layer is over the III-N channel layer in a source side access region of the device and does not extend past the gate electrode; and
the 2DEG channel extends continuously through the III-N channel layer from below the source electrode to the drain electrode and the source electrode is electrically isolated from a portion of the 2DEG channel below the source electrode when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage of the device.