US 12,266,724 B2
III-V semiconductor device with integrated power transistor and start-up circuit
Florin Udrea, Cambridge (GB); Loizos Efthymiou, Cambridge (GB); Giorgia Longobardi, Cambridge (GB); and Martin Arnold, Cambridge (GB)
Assigned to CAMBRIDGE GAN DEVICES LIMITED, Cambourne (GB)
Appl. No. 17/609,366
Filed by CAMBRIDGE GAN DEVICES LIMITED, Cambourne (GB)
PCT Filed May 7, 2020, PCT No. PCT/EP2020/062777
§ 371(c)(1), (2) Date Nov. 5, 2021,
PCT Pub. No. WO2020/225387, PCT Pub. Date Nov. 12, 2020.
Prior Publication US 2022/0310832 A1, Sep. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/778 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 27/07 (2006.01); H01L 27/085 (2006.01); H01L 27/088 (2006.01); H01L 27/095 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7787 (2013.01) [H01L 27/027 (2013.01); H01L 27/0605 (2013.01); H01L 27/0738 (2013.01); H01L 27/085 (2013.01); H01L 27/088 (2013.01); H01L 27/095 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/778 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A heterojunction chip comprising:
a III-nitride semiconductor based heterojunction power device comprising:
a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising:
a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of a second conductivity type;
a first terminal operatively connected to the first III-nitride semiconductor region;
a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region;
a first highly doped semiconductor region of a first conductivity type formed over the first III-nitride semiconductor region, and between the first terminal and the second terminal; and
a first gate region being formed over the first III-nitride semiconductor region, and between the first terminal and the second terminal; and
a second heterojunction transistor formed on the substrate, the second heterojunction transistor comprising:
a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas of the second conductivity type;
a third terminal operatively connected to the second III-nitride semiconductor region;
a fourth terminal laterally spaced from the third terminal in a first dimension and operatively connected to the second III-nitride semiconductor region;
a first plurality of highly doped semiconductor regions of a first conductivity type formed over the second III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the third terminal and the fourth terminal, wherein the first plurality of highly doped semiconductor regions comprises at least two highly doped semiconductor regions of the first conductivity type in contact with the second III-nitride semiconductor region and laterally spaced from each other in a second dimension that is perpendicular to the first dimension; and
a second gate region operatively connected to the first plurality of highly doped semiconductor regions,
wherein one of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor; and
an interface circuit operatively connected with the second heterojunction transistor,
wherein the interface circuit is monolithically integrated with any of the first or the second heterojunction transistor.