US 12,266,721 B2
Field effect transistor with multiple stepped field plate
Jia Guo, New Hill, NC (US); Kyle Bothe, Cary, NC (US); and Scott Sheppard, Chapel Hill, NC (US)
Assigned to Wolfspeed, Inc., Durham, NC (US)
Filed by Wolfspeed, Inc., Durham, NC (US)
Filed on Jun. 7, 2022, as Appl. No. 17/834,013.
Application 17/834,013 is a continuation in part of application No. 17/081,476, filed on Oct. 27, 2020, granted, now 11,502,178.
Prior Publication US 2022/0302291 A1, Sep. 22, 2022
Int. Cl. H01L 29/778 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/778 (2013.01) [H01L 29/402 (2013.01); H01L 29/66431 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01)] 27 Claims
OG exemplary drawing
 
22. A high electron mobility transistor device, comprising:
a channel layer;
a semiconductor barrier layer on the channel layer;
a surface dielectric layer on the semiconductor barrier layer;
a gate on the surface dielectric layer, wherein the surface dielectric layer comprises an aperture therein that is laterally spaced apart from the gate;
source and drain contacts on the semiconductor barrier layer, wherein the gate is between the source and drain contacts;
an interlayer dielectric layer on the surface dielectric layer, wherein the interlayer dielectric layer extends over the gate and into the aperture in the surface dielectric layer; and
a field plate on the interlayer dielectric layer between the gate and the drain contact, wherein the field plate is laterally spaced apart from the gate, wherein a recessed portion of the field plate is above the aperture in the surface dielectric layer, wherein the field plate comprises a first step adjacent the recessed portion of the field plate on a side of the field plate opposite the gate, a second step adjacent the first step;
wherein the recessed portion of the field plate is vertically spaced from the semiconductor barrier layer by a first distance, the first step is vertically spaced from the semiconductor barrier layer by a second distance, and the second step is vertically spaced from the semiconductor barrier layer by a third distance, wherein the second distance is greater than the first distance and the third distance is greater than the second distance.