US 12,266,713 B2
Transistor with dielectric spacers and method of fabrication therefor
Darrell Glenn Hill, Chandler, AZ (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on May 3, 2022, as Appl. No. 17/661,827.
Prior Publication US 2023/0361198 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/778 (2006.01); H01L 21/02 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/6656 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02178 (2013.01); H01L 29/401 (2013.01); H01L 29/402 (2013.01); H01L 29/42356 (2013.01); H01L 29/66553 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method of fabricating a transistor device, the method comprising:
providing a substrate that includes an upper surface;
forming a multi-layer dielectric stack on the upper surface of the substrate, the multi-layer dielectric stack including a first dielectric layer, a second dielectric layer, and a third dielectric layer, wherein the first dielectric layer and the third dielectric layer each have high etch selectivity with respect to the second dielectric layer;
forming a gate channel opening in the multi-layer dielectric stack through the second dielectric layer and the third dielectric layer;
forming dielectric spacers in the gate channel opening over the first dielectric layer;
extending the gate channel opening through the first dielectric layer by selectively etching a portion of the first dielectric layer;
forming a gate electrode in the gate channel opening;
forming an interlayer dielectric layer over the gate electrode and the multi-layer dielectric stack; and
forming a field plate over the interlayer dielectric layer, wherein the field plate is capacitively coupled with the gate electrode and is electrically connected to a source electrode of the transistor device.