CPC H01L 29/66553 (2013.01) [H01L 21/823431 (2013.01); H01L 29/0665 (2013.01); H01L 29/24 (2013.01); H01L 29/42356 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66969 (2013.01); H10B 61/22 (2023.02); H10B 63/30 (2023.02); H10N 50/85 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 70/24 (2023.02); H10N 70/841 (2023.02)] | 19 Claims |
14. A method of fabricating a transistor, the method comprising:
forming a material layer stack comprising a plurality of bilayers, wherein each bilayer is formed by depositing a channel layer comprising a monocrystalline transition metal dichalcogenide (TMD) on a layer of III-N material;
patterning the material layer stack into a block;
forming a dummy gate over a first portion of the block, wherein the dummy gate extends along a direction orthogonal to a length of the block;
forming a dielectric adjacent to the dummy gate and adjacent to the block;
forming a first opening in the dielectric adjacent to a first sidewall of the dummy gate and forming a second opening in the dielectric adjacent to a second sidewall of the dummy gate, wherein the second sidewall is opposite to the first sidewall;
etching and removing the layer of III-N material from the block in the first opening and in the second opening to form a plurality of channel layers;
forming a liner to clad portions of the plurality of channel layers in the first opening and in the second opening;
forming a spacer adjacent to the liner between the plurality of channel layers in the first opening and in the second opening;
forming a gate between each of plurality of channel layers adjacent to the liner after removing the dummy gate; and
forming a first metallization structure adjacent to a first end of the plurality of channel layers and a second metallization structure adjacent to a second end of the plurality of channel layer, wherein the first end and the second end are separated by the gate.
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