US 12,266,711 B2
Semiconductor device and method for fabricating the same
Beom-Yong Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Nov. 14, 2023, as Appl. No. 18/508,231.
Application 18/508,231 is a continuation of application No. 17/741,204, filed on May 10, 2022, granted, now 11,855,172.
Application 17/741,204 is a continuation of application No. 16/780,637, filed on Feb. 3, 2020, granted, now 11,342,437, issued on May 24, 2022.
Application 16/780,637 is a continuation of application No. 16/233,582, filed on Dec. 27, 2018, granted, now 10,593,777, issued on Mar. 17, 2020.
Claims priority of application No. 10-2018-0081861 (KR), filed on Jul. 13, 2018.
Prior Publication US 2024/0088257 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 29/94 (2006.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01)
CPC H01L 29/517 (2013.01) [H01L 21/28088 (2013.01); H01L 28/60 (2013.01); H01L 29/0607 (2013.01); H01L 29/4966 (2013.01); H01L 29/94 (2013.01); H10B 12/30 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A memory cell comprising:
a semiconductor substrate including a first impurity region, a second impurity region, and a word line trench formed between the first impurity region and the second impurity region;
a buried word line formed in the word line trench;
a bit line coupled to the first impurity region; and
a capacitor coupled to the second impurity region,
wherein the capacitor includes:
a bottom electrode;
a dielectric layer including a high-k material, which is formed on the bottom electrode;
a top electrode formed on the dielectric layer; and
an interface control layer formed between the dielectric layer and the top electrode, and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material that are sequentially stacked on top of one another.