| CPC H01L 29/42392 (2013.01) [H01L 27/088 (2013.01); H01L 29/0673 (2013.01); H01L 29/78696 (2013.01)] | 25 Claims |
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1. An integrated circuit structure, comprising:
a first fin structure over a first sub-fin, the first sub-fin in an isolation structure;
a second fin structure laterally spaced apart from the first fin structure, the second fin structure over a second sub-fin, the second sub-fin in the isolation structure;
a dielectric anchor in the isolation structure, the dielectric anchor laterally between and spaced apart from the first fin structure and the second fin structure;
a gate dielectric layer over the first fin structure and over the second fin structure, and the gate dielectric layer on sides of the dielectric anchor;
a gate electrode over the gate dielectric layer, the gate electrode having a first portion over the first fin structure and having a second portion over the second fin structure, wherein the dielectric anchor is laterally between the first portion of the gate electrode and the second portion of the gate electrode; and
a gate cut plug on the top surface of the dielectric anchor, the gate cut plug between the first portion of the gate electrode and the second portion of the gate electrode, wherein the gate plug is laterally offset from the dielectric anchor along a vertical axis, and wherein the gate plug has a bottommost surface above a top surface of the dielectric anchor.
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