US 12,266,707 B2
Semiconductor device with nano sheet transistor and method for fabricating the same
Yun Hyuck Ji, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jan. 4, 2022, as Appl. No. 17/568,476.
Claims priority of application No. 10-2021-0089089 (KR), filed on Jul. 7, 2021.
Prior Publication US 2023/0009388 A1, Jan. 12, 2023
Int. Cl. H01L 29/423 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823857 (2013.01); H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/4966 (2013.01); H01L 29/78696 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, the method comprising:
forming an alternating stack in which first semiconductor materials and second semiconductor materials are alternately disposed on a substrate;
forming a first sheet stack and a second sheet stack by etching the alternating stack;
forming an isolation wall between the first and second sheet stacks;
forming buried source/drain layers in the substrate to be aligned with the first and second sheet stacks;
removing the second semiconductor materials from the first sheet stack to form a first nano sheet stack of the first semiconductor materials;
removing the first semiconductor materials from the second sheet stack to form a second nano sheet stack of the second semiconductor materials;
forming a first gate and a second gate on the first nano sheet stack and the second nano sheet stack, respectively; and
forming first common source/drain layers and second common source/drain layers over the buried source/drain layers to be connected to the first nano sheet stack and the second nano sheet stack, respectively.