| CPC H01L 29/4236 (2013.01) [H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/7813 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type;
a first semiconductor region of the first conductivity type selectively in an upper layer of the first semiconductor layer;
a second semiconductor region of a second conductivity type in the upper layer of the first semiconductor layer and in contact with the first semiconductor region;
a third semiconductor region of the second conductivity type on bottom surfaces of the first and second semiconductor regions;
a plurality of gate trenches that penetrate the first and third semiconductor regions in a thickness direction of the first and third semiconductor regions, the plurality of gate trenches each comprising a bottom surface reaching an inside of the first semiconductor layer, the plurality of gate trenches being in a form of stripes and extending in one direction in a plan view and not in contact with each other at intervals;
a plurality of field-reducing regions of the second conductivity type respectively on the bottom surfaces of corresponding ones of the plurality of gate trenches;
an interlayer insulating film comprising contact openings above the first and second semiconductor regions;
a plurality of connection layers in the first semiconductor layer at intervals and each in contact with at least one sidewall of a corresponding one of the plurality of gate trenches in a second direction perpendicular to a first direction parallel with a direction in which the plurality of gate trenches extend,
the plurality of connection layers respectively electrically connects a corresponding one of the field-reducing regions to the third semiconductor region;
a first main electrode over the interlayer insulating film and filled in the contact openings; and
a second main electrode on a main surface of the first semiconductor layer, the main surface being opposite from where the first main electrode is disposed,
wherein the first semiconductor layer has an off-angle greater than 0 degrees,
the first direction is parallel with an off-direction, and
the plurality of connection layers are spaced from each other in the first direction.
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