US 12,266,702 B2
Flash memory devices with thickened source/drain silicide
Young Way Teh, Singapore (SG); Bin Zhu, Singapore (SG); Madhu Sudan Mukhopadhyay, Singapore (SG); and Subramanian Sundareswara, Singapore (SG)
Assigned to GlobalFoundries Singapore Pte. Ltd., Singapore (SG)
Filed by GlobalFoundries Singapore Pte. Ltd., Singapore (SG)
Filed on Jun. 8, 2022, as Appl. No. 17/834,982.
Prior Publication US 2023/0402516 A1, Dec. 14, 2023
Int. Cl. H01L 29/417 (2006.01); H10B 41/10 (2023.01); H10B 41/23 (2023.01); H10B 43/10 (2023.01); H10B 43/23 (2023.01); H10D 62/10 (2025.01); H10D 64/23 (2025.01)
CPC H10D 64/259 (2025.01) [H10B 41/10 (2023.02); H10B 41/23 (2023.02); H10B 43/10 (2023.02); H10B 43/23 (2023.02); H10D 62/115 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A structure for a memory device, the structure comprising:
a semiconductor substrate;
a first source/drain region in the semiconductor substrate;
a second source/drain region in the semiconductor substrate;
a first gate stack on the semiconductor substrate, the first gate stack positioned in a lateral direction between the first source/drain region and the second source/drain region, the first gate stack including a first gate electrode and a second gate electrode, and the first gate electrode including a first plurality of segments spaced apart along a longitudinal axis of the first gate stack; and
a second gate stack on the semiconductor substrate adjacent to the first gate stack, the second gate stack positioned in the lateral direction between the first source/drain region and the second source/drain region.