US 12,266,691 B2
Manufacture of power devices having increased cross over current
Siddarth Sundaresan, Dulles, VA (US); Ranbir Singh, Dulles, VA (US); and Jaehoon Park, Dulles, VA (US)
Assigned to GeneSiC Semiconductor Inc., Dulles, VA (US)
Filed by GeneSiC Semiconductor Inc., Dulles, VA (US)
Filed on Apr. 12, 2021, as Appl. No. 17/227,897.
Application 17/227,897 is a division of application No. 16/945,781, filed on Jul. 31, 2020, granted, now 11,004,940.
Prior Publication US 2022/0037470 A1, Feb. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/16 (2006.01); H01L 27/02 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/1608 (2013.01) [H01L 27/0255 (2013.01); H01L 29/4933 (2013.01); H01L 29/7804 (2013.01); H01L 29/7813 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A device comprising a unit cell on a Silicon Carbide (SiC) substrate, the unit cell comprising:
a first conductivity type source region on the SiC substrate;
a second conductivity type well region that contains the first conductivity type source region;
a first metal region in full and direct contact with a second conductivity type well contact region; and
a first silicide layer on a first side of the SiC substrate that forms a first contact for a source terminal,
a second silicide layer on a second side the SiC substrate that forms a second contact for a drain terminal,
wherein the device comprises a vertical Silicon Carbide double-implantation metal oxide semiconductor field-effect transistor (DMOSFET) comprising the drain terminal and the source terminal on the SiC substrate,
wherein the second conductivity type well contact region is within the second conductivity type well region,
wherein the first metal region is on the SiC substrate and between the first silicide layer and
wherein the source terminal and the drain terminal are at the first side and the second side of the SiC substrate, respectively.