US 12,266,689 B2
Stacked semiconductor transistor device with different conductivities having nanowire channels
Sergey Pidin, Yokohama (JP)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by SOCIONEXT INC., Kanagawa (JP)
Filed on Sep. 18, 2023, as Appl. No. 18/469,295.
Application 18/469,295 is a division of application No. 17/208,971, filed on Mar. 22, 2021, granted, now 11,798,992.
Application 17/208,971 is a continuation of application No. PCT/JP2018/035481, filed on Sep. 25, 2018.
Prior Publication US 2024/0006490 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/08 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H10B 10/00 (2023.01)
CPC H01L 29/0847 (2013.01) [H01L 27/1203 (2013.01); H01L 29/0669 (2013.01); H10B 10/12 (2023.02)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a first semiconductor layer of a first conductivity type formed on the substrate;
a second semiconductor layer of the first conductivity type formed on the substrate;
a first insulation film formed on the first semiconductor layer;
a second insulation film formed on the second semiconductor layer;
a third semiconductor layer of a second conductivity type formed on the first insulation film;
a fourth semiconductor layer of the second conductivity type formed on the second insulation film;
a first nanowire formed between the first semiconductor layer and the second semiconductor layer;
a second nanowire formed between the third semiconductor layer and the fourth semiconductor layer;
a first gate electrode formed between the first semiconductor layer and the second semiconductor layer, and between the third semiconductor layer and the fourth semiconductor layer;
a fifth semiconductor layer of a third conductivity type formed on the substrate;
a sixth semiconductor layer of the third conductivity type formed on the substrate;
a third insulation film formed on the fifth semiconductor layer;
a fourth insulation film formed on the sixth semiconductor layer;
a seventh semiconductor layer of a fourth conductivity type formed on the third insulation film;
a eighth semiconductor layer of the fourth conductivity type formed on the fourth insulation film;
a third nanowire formed between the fifth semiconductor layer and the sixth semiconductor layer;
a fourth nanowire formed between the seventh semiconductor layer and the eighth semiconductor layer;
a second gate electrode formed between the fifth semiconductor layer and the sixth semiconductor layer, and between the seventh semiconductor layer and the eighth semiconductor layer;
a first transistor including the first semiconductor layer, the second semiconductor layer, the first nanowire and the first gate electrode;
a second transistor including the third semiconductor layer, the fourth semiconductor layer, the second nanowire and the first gate electrode,
a third transistor including the fifth semiconductor layer, the sixth semiconductor layer, the third nanowire and the second gate electrode, and
a fourth transistor including the seventh semiconductor layer, the eighth semiconductor layer, the fourth nanowire and second gate electrode,
wherein the first conductivity type is different from the second conductivity type,
the third conductivity type is the same as the fourth conductivity type, and
the first transistor is formed at a same height as the third transistor, and the second transistor is formed at a same height as the fourth transistor.