US 12,266,688 B2
Semiconductor device with source/drain contact formed using bottom-up deposition
Sung-Li Wang, Hsinchu County (TW); Mrunal A. Khaderbad, Hsinchu (TW); and Yasutoshi Okuno, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jun. 8, 2023, as Appl. No. 18/331,917.
Application 17/107,471 is a division of application No. 16/252,405, filed on Jan. 18, 2019, granted, now 10,854,716, issued on Dec. 1, 2020.
Application 18/331,917 is a continuation of application No. 17/107,471, filed on Nov. 30, 2020, granted, now 11,715,763.
Claims priority of provisional application 62/711,640, filed on Jul. 30, 2018.
Prior Publication US 2023/0335592 A1, Oct. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 23/535 (2006.01); H01L 27/092 (2006.01); H01L 29/165 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01)
CPC H01L 29/0847 (2013.01) [H01L 21/0262 (2013.01); H01L 21/28518 (2013.01); H01L 21/76224 (2013.01); H01L 21/76802 (2013.01); H01L 21/76876 (2013.01); H01L 21/76883 (2013.01); H01L 21/76897 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/535 (2013.01); H01L 27/0924 (2013.01); H01L 29/165 (2013.01); H01L 29/41725 (2013.01); H01L 29/45 (2013.01); H01L 29/665 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02271 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/31116 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a first semiconductor fin and a second semiconductor fin extending from a substrate;
a first epitaxial layer wrapping around the first semiconductor fin;
a second epitaxial layer wrapping around the second semiconductor fin; and
a contact plug over the first epitaxial layer and the second epitaxial layer, the contact plug comprising a first interfacial layer over the first epitaxial layer and a second interfacial layer over the second epitaxial layer, the first and second interfacial layers comprising a noble metal element and a Group IV element, wherein the first interfacial layer is spaced apart from the first epitaxial layer at least by a metal silicide formed of a different composition than the first interfacial layer.