a substrate;

a well of a first conductivity-type over the substrate and having an anti-punch-through (APT) layer of the first conductivity-type,

a source feature and a drain feature both of a second conductivity-type over the APT layer, wherein the first conductivity-type is different than the second conductivity-type;

multiple first channel layers suspended over the APT layer and connecting the source feature to the drain feature, wherein the multiple first channel layers are vertically stacked one over another and are undoped;

a high-k metal gate wrapping around each of the first channel layers and having an interface with the APT layer, wherein a bottom surface of the source feature is below the interface;

a first source contact disposed over and electrically coupled to the source feature;

a drain contact disposed over and electrically coupled to the drain feature;

a first source via landed on the first source contact; and

a first strap via landed on a first strap contact, wherein, during a non-active mode of the semiconductor device, the first source via is configured to be coupled to ground and the first strap via is configured to be coupled to a first voltage that is lower than ground.