| CPC H01L 28/40 (2013.01) [H10B 12/0335 (2023.02)] | 20 Claims |
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1. A semiconductor device structure, comprising:
a first insulating layer formed over a semiconductor substrate;
an interconnect structure formed in the first insulating layer;
a second insulating layer formed over the first insulating layer; and
a capacitor device embedded in the second insulating layer, comprising:
a first capacitor electrode layer electrically connected to the interconnect structure;
a capacitor insulating stack formed over the first capacitor electrode layer and comprising a plurality of first layers alternatingly stacked with a plurality of second layers, wherein a dielectric constant of the first layer is different than a dielectric constant of the second layer; and
a second capacitor electrode layer formed over the capacitor insulating stack,
wherein a lowermost first layer of the first layers is in direct contact with the first capacitor electrode layer and each of the first layers is thinner than each of the second layers;
a third insulating layer separating the interconnect structure from the first capacitor electrode layer; and
a via formed in the third insulating layer and capped by the first capacitor electrode layer, wherein the via is electrically connected between the first capacitor electrode layer and the interconnect structure.
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