US 12,266,675 B2
Imaging element
Keiichi Nakazawa, Tokyo (JP); Yoshiaki Kitano, Kanagawa (JP); Hirofumi Yamashita, Kanagawa (JP); and Minoru Ishida, Tokyo (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Sep. 14, 2023, as Appl. No. 18/368,146.
Application 18/368,146 is a continuation of application No. 18/064,794, filed on Dec. 12, 2022, granted, now 11,798,972.
Application 18/064,794 is a continuation of application No. 16/956,141, granted, now 11,600,651, issued on Mar. 7, 2023, previously published as PCT/JP2018/048364, filed on Dec. 27, 2018.
Claims priority of provisional application 62/610,806, filed on Dec. 27, 2017.
Prior Publication US 2023/0420478 A1, Dec. 28, 2023
Int. Cl. H01L 27/146 (2006.01); H04N 25/75 (2023.01); H04N 25/778 (2023.01); H04N 25/79 (2023.01)
CPC H01L 27/14636 (2013.01) [H01L 27/14634 (2013.01); H04N 25/75 (2023.01); H04N 25/778 (2023.01); H04N 25/79 (2023.01)] 18 Claims
OG exemplary drawing
 
1. An imaging element, comprising:
a first section including a first semiconductor substrate, the first semiconductor substrate including a photoelectric converter and a floating diffusion;
a second section including an insulating layer and a second semiconductor substrate, the second semiconductor substrate including a readout circuit for reading out a pixel signal from the floating diffusion, wherein the readout circuit comprises:
a first transistor at least partially disposed in the second semiconductor substrate; and
a second transistor at least partially disposed in the second semiconductor substrate; and
a third section including a third semiconductor substrate, the third semiconductor substrate including a logic circuit for processing the pixel signal, wherein the second section is sandwiched between the first section and the third section; and
a through electrode that penetrates through the insulating layer and electrically connects the floating diffusion to the readout circuit, wherein the through electrode is between the first transistor and the second transistor, and wherein the second semiconductor substrate comprises a first semiconductor region and a second semiconductor region electrically isolated from the first semiconductor region by the insulating layer.