US 12,266,674 B2
Image sensor with aluminum grid pattern having openings and copper dummy patterns covering the openings
Minho Jang, Suwon-si (KR); Kyoungwon Na, Seoul (KR); Seungkuk Kang, Seoul (KR); Hyunchul Kim, Seoul (KR); Hyun Young Yeo, Hwaseong-si (KR); and In Sung Joe, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO, LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 9, 2021, as Appl. No. 17/315,321.
Claims priority of application No. 10-2020-0103288 (KR), filed on Aug. 18, 2020.
Prior Publication US 2022/0059596 A1, Feb. 24, 2022
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/14636 (2013.01) [H01L 27/14603 (2013.01); H01L 27/14643 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An image sensor, comprising:
a first chip that includes a pixel region and a pad region; and
a second chip that is connected with one surface of the first chip and includes a first connection pad, a second connection pad, second interconnection lines, and circuits that drive the first chip,
wherein the first chip comprises:
a first substrate;
an interlayer insulating layer disposed between the first substrate and the second chip;
first interconnection lines disposed in the interlayer insulating layer;
a conductive pad entirely disposed within the interlayer insulating layer in the pad region of the first chip between the second chip and the first interconnection lines;
a metal pattern disposed in the pixel region between the second chip and the first interconnection lines and disposed at a same level as the conductive pad, wherein the metal pattern is connected to the second chip by a conductive connection pad;
a third connection pad disposed between the conductive pad and the second chip;
a fourth connection pad disposed between the conductive pad and the second chip; and
a recess region formed in the pad region that penetrates the first substrate and the interlayer insulating layer and exposes the conductive pad,
wherein the conductive pad is disposed on and connected to the third connection pad and the fourth connection pad,
wherein the first connection pad is connected to the third connection pad and the second connection pad is connected to the fourth connection pad,
wherein the conductive pad is connected to the second chip through the third and first connection pads, and through the fourth and second connection pads,
wherein the first and second connection pads are connected to the second interconnection lines, and
wherein the metal pattern includes a first barrier layer disposed on its bottom surface, the conductive connection pad includes a second barrier layer disposed on its top surface and sidewall, and a connection portion of the conductive connection pad and the metal pattern has a step structure in which the second barrier layer penetrates the first barrier layer of the bottom surface of the metal pattern.