US 12,266,673 B2
Semiconductor package and method of forming the same
Chia-Lun Chang, Tainan (TW); Ching-Hua Hsieh, Hsinchu (TW); Chung-Hao Tsai, Changhua County (TW); Chung-Shi Liu, Hsinchu (TW); Chuei-Tang Wang, Taichung (TW); and Hsiu-Jen Lin, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 29, 2022, as Appl. No. 17/853,818.
Application 17/853,818 is a continuation of application No. 16/894,903, filed on Jun. 8, 2020, granted, now 11,417,698.
Claims priority of provisional application 62/953,588, filed on Dec. 26, 2019.
Prior Publication US 2022/0328552 A1, Oct. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/146 (2006.01); G02B 6/42 (2006.01); G02B 6/43 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 23/58 (2006.01)
CPC H01L 27/14634 (2013.01) [G02B 6/4253 (2013.01); G02B 6/4274 (2013.01); G02B 6/43 (2013.01); H01L 21/4857 (2013.01); H01L 21/56 (2013.01); H01L 23/3107 (2013.01); H01L 23/367 (2013.01); H01L 23/49822 (2013.01); H01L 23/58 (2013.01); H01L 27/14618 (2013.01); H01L 27/14625 (2013.01); H01L 27/14636 (2013.01); H01L 27/1469 (2013.01)] 20 Claims
OG exemplary drawing
 
7. A semiconductor package, comprising:
first and second electric integrated circuit dies;
a first insulating encapsulant laterally encapsulating the first and second electric integrated circuit dies;
a first photoelectric integrated circuit die over and electrically connected to the first electric integrated circuit die, the first photoelectric integrated circuit die comprising a first semiconductor waveguide;
a second photoelectric integrated circuit die over and electrically connected to the second electric integrated circuit die, the second photoelectric integrated circuit die comprising a second semiconductor waveguide;
a second insulating encapsulant laterally encapsulating the first and second photoelectric integrated circuit dies; and
a waveguide over the second insulating encapsulant, wherein the waveguide extends from the first semiconductor waveguide of the first photoelectric integrated circuit die to the second semiconductor waveguide of the second photoelectric integrated circuit die.