US 12,266,664 B2
Display device having an insulating layer contacting a semiconductor layer through a contact hole
Seon Young Choi, Gunpo-si (KR); Jae Hyung Cho, Suwon-si (KR); Jee Hoon Sim, Yongin-si (KR); and Jun Ki Jeong, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on Jan. 2, 2024, as Appl. No. 18/402,379.
Application 18/402,379 is a division of application No. 17/519,485, filed on Nov. 4, 2021, granted, now 11,908,874.
Claims priority of application No. 10-2021-0037418 (KR), filed on Mar. 23, 2021.
Prior Publication US 2024/0136368 A1, Apr. 25, 2024
Prior Publication US 2024/0234445 A9, Jul. 11, 2024
Int. Cl. H01L 27/12 (2006.01); G02F 1/1333 (2006.01); G02F 1/1362 (2006.01); H01L 27/15 (2006.01); H10K 59/121 (2023.01); H10K 59/124 (2023.01); H10K 102/00 (2023.01)
CPC H01L 27/1248 (2013.01) [G02F 1/133345 (2013.01); G02F 1/136227 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 27/156 (2013.01); H10K 59/1213 (2023.02); H10K 59/124 (2023.02); H10K 2102/311 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A display device comprising:
a substrate;
a polycrystalline semiconductor layer disposed on the substrate including a first electrode, a channel, and a second electrode of a driving transistor;
a first gate insulating layer disposed on the polycrystalline semiconductor layer;
a gate electrode of the driving transistor positioned on the first gate insulating layer;
a second gate insulating layer disposed on the gate electrode;
a first storage electrode positioned on the second gate insulating layer;
a first interlayer insulating layer disposed on the first storage electrode;
an oxide semiconductor layer disposed on the first interlayer insulating layer;
a second interlayer insulating layer disposed on the oxide semiconductor layer to include an opening surrounding the polycrystalline semiconductor layer and the oxide semiconductor layer;
a third interlayer insulating layer configured to fill the opening of the second interlayer insulating layer; and
a data line and a driving voltage line positioned on the third interlayer insulating layer,
wherein a portion of the polycrystalline semiconductor layer is in contact with the third interlayer insulating layer filling the opening.