US 12,266,660 B2
Memory device having 2-transistor memory cell and access line plate
Kamal M. Karda, Boise, ID (US); Karthik Sarpatwari, Boise, ID (US); Haitao Liu, Boise, ID (US); and Durai Vishak Nirmal Ramaswamy, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 29, 2023, as Appl. No. 18/400,082.
Application 18/400,082 is a continuation of application No. 17/745,298, filed on May 16, 2022, granted, now 11,871,589.
Application 17/745,298 is a continuation of application No. 17/003,077, filed on Aug. 26, 2020, granted, now 11,335,684.
Claims priority of provisional application 62/892,995, filed on Aug. 28, 2019.
Prior Publication US 2024/0138158 A1, Apr. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 99/00 (2023.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H01L 29/788 (2006.01)
CPC H01L 27/1225 (2013.01) [H01L 27/124 (2013.01); H01L 27/1251 (2013.01); H01L 29/24 (2013.01); H01L 29/78672 (2013.01); H01L 29/7869 (2013.01); H01L 29/7881 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a pillar extending in a first direction;
a first conductive region located in a first level of the apparatus, the first conductive region being separated from the pillar by a first dielectric material located in the first level, first dielectric material being adjacent the first conductive region in a second direction;
a second conductive region located in a second level of the apparatus, the second conductive region being separated from the pillar by a second dielectric material located in the second level;
a memory cell located between the first and second conductive regions and separated from the first and second conductive regions, the memory cell including a first material located in a third level of the apparatus between the first and second levels and coupled to the pillar, and a second material located in a fourth level of the apparatus between the first and second levels and coupled to the pillar, the first and second materials having different conductivity types; and
a conductive connection coupled to the first material.