| CPC H01L 27/11807 (2013.01) [H01L 2027/11824 (2013.01); H03K 19/20 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a first device comprising:
a first active region on a substrate and extending in a first direction parallel to an upper surface of the substrate,
a plurality of first channel layers provided on the first active region and configured to be spaced apart from each other in a direction perpendicular to the upper surface of the substrate,
a second active region spaced apart from and extending in parallel with the first active region,
a plurality of second channel layers provided on the second active region and configured to be spaced apart from each other in the direction perpendicular to the upper surface of the substrate,
at least one first gate structure crossing the first active region and the second active region and extending in a second direction,
a first source/drain region provided on the first active region on at least one side of the at least one first gate structure, and
a second source/drain region provided on the second active region on at least one side of the at least one first gate structure;
a second device comprising:
a third active region on the substrate and extending in the first direction,
a plurality of third channel layers provided on the third active region and configured to be spaced apart from each other in the direction perpendicular to the upper surface of the substrate,
a fourth active region spaced apart from and extending in parallel with the third active region,
a plurality of fourth channel layers provided on the fourth active region and configured to be spaced apart from each other in the direction perpendicular to the upper surface of the substrate,
second gate structures crossing the third active region and the fourth active region and extending in parallel with each other in the second direction,
a third source/drain region provided on the third active region on at least one side of the second gate structures, and
a fourth source/drain region provided on the fourth active region on at least one side of the second gate structures; and
a third device comprising:
a fifth active region on the substrate and extending in the first direction,
a plurality of fifth channel layers provided on the fifth active region and configured to be spaced apart from each other in the direction perpendicular to the upper surface of the substrate,
a sixth active region spaced apart from and extending in parallel with the fifth active region,
a plurality of sixth channel layers provided on the sixth active region configured to be spaced apart from each other in the direction perpendicular to the upper surface of the substrate,
third gate structures crossing the fifth active region and the sixth active region and extending in parallel with each other in the second direction,
a fifth source/drain region provided on the fifth active region on at least one side of the third gate structures, and
a sixth source/drain region provided on the sixth active region on at least one side of the third gate structures,
wherein a first width of the first active region is wider than a second width of the second active region,
wherein a third width of the third active region is wider than a fourth width of the fourth active region, and
wherein a fifth width of the fifth active region is substantially equal to a sixth width of the sixth active region.
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