US 12,266,658 B2
Semiconductor devices with backside contacts and isolation
Chun-Yuan Chen, Hsinchu (TW); Huan-Chieh Su, Changhua County (TW); Cheng-Chi Chuang, New Taipei (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 21, 2023, as Appl. No. 18/356,677.
Application 18/356,677 is a continuation of application No. 17/873,858, filed on Jul. 26, 2022, granted, now 11,710,742.
Application 17/873,858 is a continuation of application No. 17/104,351, filed on Nov. 25, 2020, granted, now 11,430,789, issued on Aug. 30, 2022.
Prior Publication US 2024/0021616 A1, Jan. 18, 2024
Int. Cl. H01L 27/092 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 29/0653 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
an isolation structure;
a source/drain region over the isolation structure;
a gate structure over the isolation structure and adjacent to the source/drain region;
an interconnect layer over the source/drain region and the gate structure;
an isolating layer below the gate structure;
a contact structure under the source/drain region and having a first portion and a second portion, wherein the first portion is below the second portion, wherein the second portion extends through the isolating layer and protrudes above the isolating layer, wherein a portion of the isolating layer is vertically between the gate structure and the first portion of the contact structure; and
a dielectric fin disposed on the isolation structure, wherein a bottom surface of the dielectric fin is above a bottom surface of the isolating layer.