US 12,266,656 B2
Semiconductor device and method for fabricating the same
Mun Hyeon Kim, Hwaseong-si (KR); Sung Min Kim, Incheon (KR); and Dae Won Ha, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 24, 2021, as Appl. No. 17/210,751.
Claims priority of application No. 10-2020-0095308 (KR), filed on Jul. 30, 2020.
Prior Publication US 2022/0037319 A1, Feb. 3, 2022
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/823807 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/7848 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate including a first region and a second region separated from each other;
a laminate structure including at least one sacrificial layer and at least one semiconductor layer alternately stacked on the substrate;
a first isolation insulating layer on the laminate structure on the first region, the laminate structure being between the substrate and the first isolation insulating layer;
a second isolation insulating layer on the laminate structure on the second region, the laminate structure being between the substrate and the second isolation insulating layer, and the second isolation insulating layer having a substantially same thickness as the first isolation insulating layer;
a first pattern including a first upper pattern and a first lower pattern, and extending in a first direction, the first upper pattern spaced apart from the first isolation insulating layer,
the first lower pattern directly on the first isolation insulating layer, the first lower pattern being between the first isolation insulating layer and the first upper pattern;
a first gate electrode surrounding at least a portion of the first pattern and extending in a second direction crossing the first direction, the first lower pattern partially overlapping with the first gate electrode in the second direction;
a first source/drain region on a side surface of the first gate electrode;
a second pattern including a second upper pattern and a second lower pattern, and extending in the first direction, the second upper pattern spaced apart from the second isolation insulating layer,
the second lower pattern directly on the second isolation insulating layer, the second lower pattern being between the second isolation insulating layer and the second upper pattern;
a second gate electrode surrounding at least a portion of the second pattern and extending in the second direction, the second lower pattern partially overlapping with the second gate electrode in the second direction; and
a second source/drain region on a side surface of the second gate electrode,
wherein a top surface of the first isolation insulating layer and a top surface of the second isolation insulating layer are at different heights relative to a bottom of the substrate, and
wherein each of the first isolation insulating layer and the second isolation insulating layer includes a material different from the at least one sacrificial layer, the at least one semiconductor layer, the first pattern and the second pattern.