US 12,266,653 B2
Semiconductor structure and methods of forming the same
Ta-Chun Lin, Hsinchu (TW); Kuo-Hua Pan, Hsinchu (TW); and Jhon Jhy Liaw, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 22, 2023, as Appl. No. 18/225,114.
Application 18/225,114 is a continuation of application No. 17/381,435, filed on Jul. 21, 2021, granted, now 11,749,677.
Claims priority of provisional application 63/175,017, filed on Apr. 14, 2021.
Prior Publication US 2023/0361114 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01)
CPC H01L 27/088 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a first semiconductor device formed over a substrate comprising:
a first source/drain feature over the substrate;
a first gate structure over the substrate;
a first conductive feature over the first source/drain feature; and
a first insulation layer between the first gate structure and the first conductive feature, wherein the first insulation layer comprises a first contact etching stop layer (CESL) in contact with the first source/drain feature; and
a second semiconductor device formed over the substrate comprising:
a second source/drain feature over the substrate;
a second gate structure over the substrate;
a second conductive feature over the second source/drain feature; and
a second insulation layer between the second gate structure and the second conductive feature, the second insulation layer comprises a second CESL in contact with the second source/drain feature,
wherein a thickness of the first CESL is less than a thickness of the second CESL.