US 12,266,650 B2
Stacked dies and methods for forming bonded structures
Cyprian Emeka Uzoh, San Jose, CA (US); Arkalgud R. Sitaram, Cupertino, CA (US); and Paul Enquist, Cary, NC (US)
Assigned to ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US)
Filed by ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US)
Filed on Dec. 28, 2023, as Appl. No. 18/399,478.
Application 18/399,478 is a continuation of application No. 18/145,282, filed on Dec. 22, 2022, granted, now 12,113,056.
Application 18/145,282 is a continuation of application No. 17/131,329, filed on Dec. 22, 2020, granted, now 11,658,173, issued on May 23, 2023.
Application 17/131,329 is a continuation of application No. 16/270,466, filed on Feb. 7, 2019, granted, now 10,879,226, issued on Dec. 29, 2020.
Application 16/270,466 is a continuation of application No. 15/159,649, filed on May 19, 2016, granted, now 10,204,893, issued on Feb. 12, 2019.
Prior Publication US 2024/0145458 A1, May 2, 2024
Int. Cl. H01L 25/00 (2006.01); H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/50 (2013.01) [H01L 21/304 (2013.01); H01L 21/306 (2013.01); H01L 21/3081 (2013.01); H01L 21/561 (2013.01); H01L 21/683 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/351 (2013.01); H01L 2924/3511 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A bonded structure of stacked dies, comprising:
a first integrated device die, wherein the first integrated device die comprises an upper surface opposite a lower surface and a side surface between the upper and lower surfaces of the first integrated device die and wherein the upper surface comprises first conductive features and a first nonconductive region in which the first conductive features are at least partially embedded;
a second integrated device die directly bonded to the upper surface of the first integrated device die without an intervening adhesive, wherein the second integrated device die comprises an upper surface opposite a lower surface and a side surface between the lower and upper surfaces of the second integrated device die, wherein the lower surface comprises second conductive features and a second nonconductive region in which the second conductive features are at least partially embedded, and wherein the first conductive features of the first integrated device die are directly bonded to the second conductive features of the second integrated device die and the first nonconductive region of the first integrated device die is directly bonded to the second nonconductive region of the lower surface of the second integrated device die; and
a protective material disposed on the side surfaces of the first and second integrated device dies, wherein the protective material has an outer surface characteristic of singulation after forming the protective material and after directly bonding the second integrated device die to the upper surface of the first integrated device die, the protective material comprising a polymer material.