US 12,266,647 B2
3D stacked integrated circuits having functional blocks configured to provide redundancy sites
Tony M. Brewer, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 12, 2022, as Appl. No. 17/964,332.
Application 17/964,332 is a continuation of application No. 17/219,202, filed on Mar. 31, 2021, granted, now 11,488,945.
Application 17/219,202 is a continuation of application No. 16/909,873, filed on Jun. 23, 2020, granted, now 10,991,684, issued on Apr. 27, 2021.
Application 16/909,873 is a continuation of application No. 16/218,901, filed on Dec. 13, 2018, granted, now 10,707,197, issued on Jul. 7, 2020.
Prior Publication US 2023/0033072 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/18 (2023.01); G11C 29/00 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 25/065 (2023.01); H01L 27/06 (2006.01); H01L 27/118 (2006.01); G06F 11/16 (2006.01); G06F 11/20 (2006.01); G11C 29/14 (2006.01); G11C 29/44 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/18 (2013.01) [G11C 29/74 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01); H01L 27/118 (2013.01); G06F 11/1666 (2013.01); G06F 11/2023 (2013.01); G11C 29/14 (2013.01); G11C 29/4401 (2013.01); G11C 29/88 (2013.01); H01L 25/50 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a plurality of functional blocks of memory and a logic circuit configured to perform a task using the functional blocks of memory;
wherein the integrated circuit is configured to identify, among the functional blocks, a first functional block and set up a second functional block to perform a task.