US 12,266,639 B2
Method of fabricating semiconductor package
Hao-Yi Tsai, Hsinchu (TW); Cheng-Chieh Hsieh, Tainan (TW); Tsung-Hsien Chiang, Hsinchu (TW); Hui-Chun Chiang, Hsinchu (TW); Tzu-Sung Huang, Tainan (TW); Ming-Hung Tseng, Miaoli County (TW); Kris Lipu Chuang, Hsinchu (TW); Chung-Ming Weng, Taichung (TW); Tsung-Yuan Yu, Taipei (TW); and Tzuan-Horng Liu, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 1, 2023, as Appl. No. 18/363,731.
Application 18/363,731 is a division of application No. 17/460,340, filed on Aug. 30, 2021, granted, now 11,935,871.
Prior Publication US 2023/0378140 A1, Nov. 23, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 24/02 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 24/06 (2013.01); H01L 24/73 (2013.01); H01L 2224/02141 (2013.01); H01L 2224/0311 (2013.01); H01L 2224/0312 (2013.01); H01L 2224/05559 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/06135 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor package, comprising:
bonding a first semiconductor substrate having a through substrate via to a second semiconductor substrate;
encapsulating the first semiconductor substrate using a first insulating encapsulation on the second semiconductor substrate;
removing a portion of the first semiconductor substrate until revealing a portion of the through substrate via and forming a concave structure laterally spaced from the first insulating encapsulation by a portion of the first semiconductor substrate while the portion of the first semiconductor substrate and the first insulating encapsulation are covered by a protection layer;
forming a dielectric layer structure on the first semiconductor substrate and the first insulating encapsulation;
forming a conductor structure extending through the dielectric layer structure and electrically connected to the through substrate via; and
forming a second insulating encapsulation in contact with a side edge of the second semiconductor substrate, a side edge of the first insulting encapsulation, and a side edge of the dielectric layer structure.