US 12,266,637 B2
Die stack structure and manufacturing method thereof
Hsien-Wei Chen, Hsinchu (TW); Jie Chen, New Taipei (TW); Ming-Fa Chen, Taichung (TW); Sung-Feng Yeh, Taipei (TW); and Ying-Ju Chen, Yunlin County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 8, 2022, as Appl. No. 17/715,963.
Application 17/715,963 is a continuation of application No. 17/026,274, filed on Sep. 20, 2020, granted, now 11,309,291.
Prior Publication US 2022/0230996 A1, Jul. 21, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 23/3107 (2013.01); H01L 23/5386 (2013.01); H01L 24/06 (2013.01); H01L 24/80 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A die stack structure, comprising:
an interconnection structure;
a logic die electrically connected to the interconnection structure, wherein the logic die comprises a first dielectric bonding structure;
a control die laterally separated from the logic die and electrically connected to the interconnection structure;
a dummy die disposed on the logic die, wherein the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure; and
a memory cube disposed on and electrically connected to the control die.