US 12,266,632 B2
Package process and package structure
Chi-Chih Shen, Kaohsiung (TW); Jen-Chuan Chen, Kaohsiung (TW); and Tommy Pan, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on Jan. 11, 2022, as Appl. No. 17/573,593.
Application 14/087,454 is a division of application No. 12/711,870, filed on Feb. 24, 2010, granted, now 8,618,645, issued on Dec. 31, 2013.
Application 17/573,593 is a continuation of application No. 15/620,692, filed on Jun. 12, 2017, granted, now 11,222,866.
Application 15/620,692 is a continuation of application No. 14/087,454, filed on Nov. 22, 2013, granted, now 9,698,120, issued on Jul. 4, 2017.
Claims priority of application No. 98133269 (TW), filed on Sep. 30, 2009.
Prior Publication US 2022/0157775 A1, May 19, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/96 (2013.01) [H01L 21/561 (2013.01); H01L 21/6835 (2013.01); H01L 21/76898 (2013.01); H01L 23/3135 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/6835 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/73203 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/91 (2013.01); H01L 2224/95001 (2013.01); H01L 2224/96 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06572 (2013.01); H01L 2924/01023 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/014 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a first semiconductor device;
a second semiconductor device disposed over the first semiconductor device;
a conductive bump connected to the first semiconductor device and the second semiconductor device;
a first underfill disposed between the first semiconductor device and the second semiconductor device, and covering a lateral surface of the conductive bump;
a second molding compound covering the second semiconductor device and a lateral surface of the first underfill, wherein the second molding compound is spaced apart from the first semiconductor device;
a second underfill disposed under the first semiconductor device, wherein at least a portion of the second underfill is spaced apart from a lateral surface of the first semiconductor device; and
a third molding compound covering a lateral surface of the second semiconductor device and laterally overlapping the second underfill.