US 12,266,631 B2
Flip-chip package assembly
Rafael Jose Lizares Guevara, Angeles (PH); John Carlo Cruz Molina, Limay (PH); and Steffany Ann Lacierda Moreno, Bamban (PH)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Apr. 25, 2023, as Appl. No. 18/306,832.
Application 18/306,832 is a division of application No. 17/219,453, filed on Mar. 31, 2021, granted, now 11,637,083.
Prior Publication US 2023/0260958 A1, Aug. 17, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01)
CPC H01L 24/81 (2013.01) [H01L 21/4828 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 2224/13019 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16258 (2013.01); H01L 2224/81024 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/17747 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a package substrate having a planar die mount surface;
cavities extending into the planar die mount surface;
solder pads formed in the cavities, the solder pads corresponding to locations of post connects on a semiconductor die to be mounted to the package substrate; and
a semiconductor die having bond pads over an active surface, and having post connects corresponding to the bond pads with a proximal end on a bond pad and extending to a distal end, the semiconductor die mounted to the package substrate by forming solder joints between the distal end of the post connects and the solder pads of the package substrate, wherein the distal end includes a dished feature.