US 12,266,630 B2
Bond pad connection layout
Bharat Bhushan, Taichung (TW); Pratap Murali, Meridian, ID (US); Raj K. Bansal, Boise, ID (US); and David A. Daycock, Singapore (SG)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Jan. 5, 2024, as Appl. No. 18/405,875.
Application 18/405,875 is a continuation of application No. 17/956,797, filed on Sep. 29, 2022, granted, now 11,876,068.
Application 17/956,797 is a continuation of application No. 17/103,834, filed on Nov. 24, 2020, granted, now 11,502,053, issued on Nov. 15, 2022.
Prior Publication US 2024/0145425 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 25/18 (2023.01)
CPC H01L 24/49 (2013.01) [H01L 24/06 (2013.01); H01L 25/18 (2013.01); H01L 2924/15165 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor die, comprising:
a substrate layer;
a component layer disposed on the substrate layer, the component layer comprising component blocks that are separated by slits arranged in a first direction; and
a plurality of bond pads aligned in a second direction that is perpendicular to the first direction,
wherein the slits extend in a third direction from a top surface of the component layer to the substrate layer.