US 12,266,624 B2
Semiconductor die with solder restraining wall
John Carlo Cruz Molina, Limay (PH); and Rafael Jose Lizares Guevara, Manila (PH)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Sep. 29, 2021, as Appl. No. 17/488,715.
Prior Publication US 2023/0106976 A1, Apr. 6, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01)
CPC H01L 24/16 (2013.01) [H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 24/48 (2013.01); H01L 2224/02235 (2013.01); H01L 2224/0225 (2013.01); H01L 2224/02255 (2013.01); H01L 2224/0226 (2013.01); H01L 2224/03013 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/06131 (2013.01); H01L 2224/10126 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/48247 (2013.01)] 22 Claims
OG exemplary drawing
 
16. A semiconductor device, comprising:
a package substrate;
a semiconductor die including a semiconductor surface comprising circuitry electrically connected to top-level bond pads, the top-level bond pads including inner bond pads and outer bond pads positioned beyond the inner bond pads, with solder on at least the inner bond pads, with the semiconductor die attached to the package substrate;
a ring structure positioned around a location of at least the inner bond pads;
wherein the package substrate comprises a leadframe including a die pad and a plurality of leads, wherein the semiconductor die comprises a wafer chip scale package (WCSP) die including a redirect layer (RDL) that provides the inner bond pads and the outer bond pads which are both electrically connected to die bond pads that are electrically connected to the circuitry, the WCSP die attached top side up on the die pad;
wherein the ring structure comprises copper;
further comprising bond wires between the outer bond pads and the plurality of leads; and
wherein the top semiconductor package or the top die is electrically connected exclusively to only the solder on the inner bond pads.