US 12,266,617 B2
Chip package, electronic device, and chip package preparation method
Nan Zhao, Shenzhen (CN); Chunghsuan Tsai, Shenzhen (CN); and Shanghsuan Chiang, Shenzhen (CN)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed on May 17, 2022, as Appl. No. 17/746,186.
Application 17/746,186 is a continuation of application No. PCT/CN2019/120325, filed on Nov. 22, 2019.
Prior Publication US 2022/0278056 A1, Sep. 1, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/562 (2013.01) [H01L 21/56 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 24/32 (2013.01); H01L 25/0655 (2013.01); H01L 2224/32225 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip package, comprising:
a substrate;
a first die;
a second die, wherein the first die and the second die are disposed on a side of the substrate, and the first die and the second die are separately electrically connected to the substrate; and
a beam structure, disposed between the first die and the second die, wherein a first end of the beam structure is stacked with a part of the first die, a second end of the beam structure is stacked with a part of the second die, the beam structure is separately insulated from the first die and the second die, and a thermal expansion coefficient of the beam structure is less than a thermal expansion coefficient of the substrate.