US 12,266,608 B2
Integrated photonics and processor package with redistribution layer and EMIB connector
Susheel Jadhav, Chandler, AZ (US); Kenneth Brown, Tempe, AZ (US); David Hui, Santa Clara, CA (US); Ling Liao, Fremont, CA (US); and Syed S. Islam, Cupertino, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 25, 2020, as Appl. No. 17/104,963.
Claims priority of provisional application 63/044,242, filed on Jun. 25, 2020.
Prior Publication US 2021/0407909 A1, Dec. 30, 2021
Int. Cl. H01L 23/538 (2006.01); G02B 6/42 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/5381 (2013.01) [G02B 6/423 (2013.01); G02B 6/4268 (2013.01); G02B 6/4274 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A package comprising:
a substrate;
an interconnect bridge on the substrate;
a redistribution layer (RDL) having a top side and a bottom side opposite the top side, wherein the bottom side of the RDL is on the interconnect bridge and electrically coupled with the interconnect bridge;
a photonic integrated circuit (PIC) coupled to the top side of the RDL, wherein the PIC is electrically coupled with the interconnect bridge;
an electrical integrated circuit (EIC) that is electrically coupled with the RDL, the PIC, and the interconnect bridge, wherein the EIC is vertically intervening between the PIC and the RDL; and
a processing unit on the interconnect bridge, wherein the PIC and the processing unit are electrically coupled through the RDL and the interconnect bridge.
 
11. A system comprising:
a package comprising:
a substrate;
an interconnect bridge on the substrate;
a redistribution layer (RDL) having a top side and a bottom side opposite the top side, wherein the bottom side of the RDL is on the interconnect bridge and electrically coupled with the interconnect bridge;
a photonic integrated circuit (PIC) coupled to the top side of the RDL, wherein the PIC is electrically coupled with the interconnect bridge;
a central processing unit on the interconnect bridge, wherein the PIC and the central processing unit are electrically coupled through the RDL and the interconnect bridge, wherein an electrical connection on the bottom side of the RDL is electrically coupled with the PIC and wherein the electrical connection is outside a footprint of the PIC in relation to the RDL; and
an electrical integrated circuit (EIC) electrically coupled with the RDL, the PIC, and the interconnect bridge, wherein the EIC is vertically intervening between the PIC and the RDL; and
a fiber-optic cable optically coupled with a portion of the PIC extending laterally beyond the RDL.