US 12,266,606 B2
Semiconductor device with backside spacer and methods of forming the same
Po-Yu Huang, Hsinchu (TW); Chia-Hsien Yao, Hsinchu (TW); Fu-Kai Yang, Hsinchu (TW); and Mei-Yun Wang, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 20, 2023, as Appl. No. 18/355,993.
Application 17/694,135 is a division of application No. 16/935,368, filed on Jul. 22, 2020, granted, now 11,276,643.
Application 18/355,993 is a continuation of application No. 17/694,135, filed on Mar. 14, 2022, granted, now 11,721,626.
Prior Publication US 2023/0369223 A1, Nov. 16, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 23/5286 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0847 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a backside interconnect structure;
a bottom dielectric layer disposed over the backside interconnect structure;
a bottom semiconductor layer disposed over the bottom dielectric layer;
a first plurality of nanostructures and a second plurality of nanostructures disposed over the bottom semiconductor layer;
a source/drain feature sandwiched between and in contact with sidewalls of the first plurality of nanostructures and sidewalls of the second plurality of nanostructures; and
a backside via extending from the backside interconnect structure through the bottom dielectric layer and the bottom semiconductor layer to electrically couple to the source/drain feature by way of a silicide layer,
wherein a sidewall of the backside via is spaced apart from the sidewalls of the bottom semiconductor layer by a backside spacer.