	US 12,266,602 B2
	Integrated circuit structure and method for forming the same
Shih-Yen Lin, New Taipei (TW); Yu-Wei Zhang, Hualien County (TW); Kuan-Chao Chen, Tainan (TW); Si-Chen Lee, Taipei (TW); and Chi Chen, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and NATIONAL TAIWAN UNIVERSITY, Taipei (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and NATIONAL TAIWAN UNIVERSITY, Taipei (TW)
Filed on Jan. 10, 2022, as Appl. No. 17/572,160.
Claims priority of provisional application 63/222,792, filed on Jul. 16, 2021.
Prior Publication US 2023/0014503 A1, Jan. 19, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01)

CPC H01L 23/5226 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 29/66545 (2013.01)]

20 Claims

1. A method, comprising:

forming a transistor over a substrate;

forming an interlayer dielectric (ILD) layer over the transistor;

forming a first inter-metal dielectric (IMD) layer over the ILD layer;

etching a via opening extending through the first IMD layer;

forming a first 2-D material layer lining along sides and a bottom of the via opening;

depositing a first metal in the via opening and over the first 2-D material layer;

performing a chemical mechanism polishing (CMP) process to the first metal until the first IMD layer is exposed;

forming a second IMD layer over the first IMD layer;

etching a trench in the second IMD layer;

forming a second 2-D material layer lining along sides and a bottom of the trench; and

depositing a second metal over the second 2-D material layer at a temperature lower than a temperature of depositing the first metal over the first 2-D material layer.