| CPC H01L 23/49838 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49822 (2013.01); H05K 1/0228 (2013.01); H05K 1/0243 (2013.01); H05K 1/0298 (2013.01); H05K 1/111 (2013.01); H05K 1/181 (2013.01); H05K 1/0237 (2013.01); H05K 1/0284 (2013.01)] | 20 Claims |

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1. An integrated circuit (IC) interconnect package comprising:
a substrate core;
a plurality of buildup layers disposed above and below the substrate core, wherein the plurality of buildup layers comprises:
a top layer disposed above the substrate core, the top layer comprising a plurality of contacts to electrically and mechanically connect to a chip or die;
a second layer comprising a plurality of signal lines; and
a bottom layer disposed below the substrate core, the bottom layer comprising a plurality of Land Grid Array (LGA) contacts;
a plurality of interconnect vias extending vertically through the substrate core, the plurality of interconnect vias connecting the plurality of contacts with the plurality of LGA contacts through a plurality of micro-vias,
wherein a differential signal via pair of the plurality of interconnect vias comprises a first via and a second via that are electrically connected to a respective LGA contact of the plurality of LGA contacts, each of the first via and the second via at least partly overlapping with the respective LGA contact and offset inwardly from a center axis of the respective LGA contact, and
wherein, for each via of the first via and the second via, a respective two or more signal lines of the plurality of signal lines overlap with the respective LGA contact without overlapping the via.
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