US 12,266,594 B2
Method of making semiconductor device having self-aligned interconnect structure
Chih-Yu Lai, Hsinchu (TW); Chih-Liang Chen, Hsinchu (TW); Chi-Yu Lu, Hsinchu (TW); Shang-Syuan Ciou, Hsinchu (TW); Hui-Zhong Zhuang, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); and Shang-Wen Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Nov. 22, 2023, as Appl. No. 18/517,298.
Application 18/517,298 is a division of application No. 17/231,527, filed on Apr. 15, 2021, granted, now 11,854,940.
Prior Publication US 2024/0096756 A1, Mar. 21, 2024
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76897 (2013.01); H01L 21/76898 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of making a semiconductor device, comprising:
manufacturing a first transistor over a first side of a substrate;
depositing a spacer material against a sidewall of the first transistor;
recessing the spacer material to expose a first portion of the sidewall of the first transistor;
manufacturing a first electrical connection to the transistor, a first portion of the first electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the first electrical connection contacts the first portion of the sidewall of the first transistor; and
manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.