US 12,266,593 B2
Method of forming semiconductor device having at least one via including concave portions on sidewall
Ting-Li Yang, Tainan (TW); Wen-Hsiung Lu, Tainan (TW); Jhao-Yi Wang, Tainan (TW); Fu Wei Liu, Hsincu (TW); and Chin-Yu Ku, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 2, 2023, as Appl. No. 18/363,733.
Application 18/363,733 is a division of application No. 17/461,972, filed on Aug. 30, 2021, granted, now 11,942,398.
Prior Publication US 2023/0395468 A1, Dec. 7, 2023
Int. Cl. H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/486 (2013.01); H01L 21/76879 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, comprising:
providing a substrate;
forming at least one via penetrating through the substrate, wherein the at least one via comprises a plurality of concave portions on a sidewall thereof;
forming a liner layer filling in the plurality of concave portions of the at least one via; and
performing a cyclic deposition and etching process to form a conductive layer on the sidewall of the at least one via, covering the liner layer, and extending onto a surface of the substrate, wherein a thickness of the conductive layer on the sidewall of the at least one via is varied.