US 12,266,592 B2
Through vias of semiconductor structure and method of forming thereof
Yuan-Yang Hsiao, Taipei (TW); Dian-Hau Chen, Hsinchu (TW); and Yen-Ming Chen, Chu-Pei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 26, 2023, as Appl. No. 18/324,643.
Application 18/324,643 is a continuation of application No. 17/363,519, filed on Jun. 30, 2021, granted, now 11,705,384.
Claims priority of provisional application 63/168,385, filed on Mar. 31, 2021.
Prior Publication US 2023/0298972 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/482 (2006.01); H01L 23/485 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76898 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, the method comprising:
forming a first portion of an interconnect structure over a substrate, the first portion of the interconnect structure comprising a first metallization layer over the substrate, and a second metallization layer over the first metallization layer;
forming a first through via through the first portion of the interconnect structure;
forming a second portion of the interconnect structure over the first portion of the interconnect structure, the second portion of the interconnect structure comprising a third metallization layer over the second metallization layer and a fourth metallization layer over the third metallization layer;
forming a second through via through the second portion of the interconnect structure, the second through via contacting the first through via;
thinning the substrate to expose the first through via; and
forming an external contact on the first through via.