US 12,266,590 B2
Dual side direct cooling semiconductor package
Inpil Yoo, Bavaria (DE); Jerome Teysseyre, Scottsdale, AZ (US); Oseob Jeon, Seoul (KR); Keunhyuk Lee, Suzhou (CN); and Michael J. Seddon, Gilbert, AZ (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Jun. 15, 2022, as Appl. No. 17/806,961.
Claims priority of provisional application 63/203,235, filed on Jul. 14, 2021.
Prior Publication US 2023/0019930 A1, Jan. 19, 2023
Int. Cl. H01L 23/44 (2006.01); H01L 23/40 (2006.01); H05K 7/20 (2006.01)
CPC H01L 23/44 (2013.01) [H05K 7/20236 (2013.01); H01L 2023/405 (2013.01); H01L 2023/4056 (2013.01); H01L 2023/4068 (2013.01); H01L 2023/4087 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
one or more power semiconductor die comprised in a die module;
a first heat sink directly coupled to one or more source pads of the die module;
a second heat sink directly coupled to one or more drain pads of the die module;
a gate contact coupled with one or more gate pads of the die module; and
a coating coupled directly to the die module;
wherein the gate contact is configured to extend through an immersion cooling enclosure.