US 12,266,589 B2
Enhanced base die heat path using through-silicon vias
Weston Bertrand, Tempe, AZ (US); Kyle Arrington, Gilbert, AZ (US); Shankar Devasenathipathy, Tempe, AZ (US); Aaron McCann, Queen Creek, AZ (US); Nicholas Neal, Gilbert, AZ (US); and Zhimin Wan, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 15, 2024, as Appl. No. 18/635,894.
Application 18/635,894 is a continuation of application No. 18/088,478, filed on Dec. 23, 2022, granted, now 12,057,369.
Application 18/088,478 is a continuation of application No. 16/794,789, filed on Feb. 19, 2020, granted, now 11,854,935, issued on Dec. 26, 2023.
Prior Publication US 2024/0282667 A1, Aug. 22, 2024
Int. Cl. H01L 23/433 (2006.01); H01L 23/367 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/433 (2013.01) [H01L 23/3675 (2013.01); H01L 25/0657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A stacked die package, comprising:
a substrate;
a base die coupled to the substrate by solder;
a top die vertically over the base die, the top die coupled to the base die with interconnects, the top die having a first sidewall and a second sidewall, the second sidewall laterally opposite the first sidewall;
a first dummy die laterally spaced apart from the first sidewall of the top die, the first dummy die vertically over the base die, and the first dummy die comprising silicon;
a second dummy die laterally spaced apart from the second sidewall of the top die, the second dummy die vertically over the base die, and the second dummy die comprising silicon; and
an interface material layer continuous over and directly on the top die, the first dummy die and the second dummy die.