US 12,266,586 B2
Double-sided coolable semiconductor package
Juergen Hoegerl, Regensburg (DE); Ordwin Haase, Taufkirchen (DE); and Tobias Kist, Effeltrich (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Jun. 20, 2022, as Appl. No. 17/844,455.
Application 17/844,455 is a continuation of application No. 17/147,717, filed on Jan. 13, 2021, granted, now 11,515,228.
Application 17/147,717 is a continuation of application No. 16/520,058, filed on Jul. 23, 2019, granted, now 11,018,072, issued on May 25, 2021.
Claims priority of application No. 102018212439.6 (DE), filed on Jul. 25, 2018; and application No. 102018126972.2 (DE), filed on Oct. 29, 2018.
Prior Publication US 2022/0319948 A1, Oct. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/367 (2006.01); H01L 21/52 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 23/433 (2006.01); H01L 23/492 (2006.01); H01L 23/495 (2006.01); H01L 25/16 (2023.01); H01L 29/16 (2006.01); H10D 62/832 (2025.01)
CPC H01L 23/367 (2013.01) [H01L 21/52 (2013.01); H01L 21/56 (2013.01); H01L 23/3121 (2013.01); H01L 23/3735 (2013.01); H01L 23/433 (2013.01); H01L 23/492 (2013.01); H01L 23/49524 (2013.01); H01L 25/16 (2013.01); H10D 62/8325 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A double-sided coolable semiconductor package, comprising:
an encapsulant body of electrically insulating mold compound;
a first electrically conductive element having an outwardly exposed metal surface that is exposed from a first side of the encapsulant body;
a first carrier substrate having a first electrically conductive layer, a second electrically conductive layer having an outwardly exposed surface that is exposed from a second side of the encapsulant body that is opposite from the first side, and an electrical insulation layer arranged between the first and second electrically conductive layers;
a first electrically conductive spacer arranged between the first electrically conductive element and the first electrically conductive layer;
a power semiconductor chip arranged between the first electrically conductive element and the first electrically conductive layer; and
a second electrically conductive spacer arranged between the first electrically conductive element and the power semiconductor chip,
wherein a first carrier region of the first electrically conductive layer of the first carrier substrate is electrically connected to a first power terminal of the double-sided coolable semiconductor package,
wherein a second carrier region of the first electrically conductive layer of the first carrier substrate is arranged alongside the first carrier region and is electrically connected to a second power terminal of the double-sided coolable semiconductor package,
wherein a first region of the first electrically conductive element is connected to a third power terminal of the double-sided coolable semiconductor package.