US 12,266,585 B2
Arrangement and thermal management of 3D stacked dies
John Wuu, Fort Collins, CO (US); Samuel Naffziger, Fort Collins, CO (US); Patrick J. Shyvers, Fort Collins, CO (US); Milind S. Bhagavat, Broomfield, CO (US); Kaushik Mysore, Austin, TX (US); and Brett P. Wilkerson, Austin, TX (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Nov. 2, 2021, as Appl. No. 17/516,988.
Application 17/516,988 is a division of application No. 16/563,077, filed on Sep. 6, 2019, granted, now 11,164,807.
Application 16/563,077 is a continuation of application No. 15/686,558, filed on Aug. 25, 2017, granted, now 10,431,517.
Prior Publication US 2022/0059425 A1, Feb. 24, 2022
Int. Cl. H01L 23/367 (2006.01); H01L 23/36 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 23/373 (2006.01)
CPC H01L 23/367 (2013.01) [H01L 23/36 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 23/373 (2013.01); H01L 23/3732 (2013.01); H01L 23/3736 (2013.01); H01L 23/3737 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor chip device, comprising:
a first semiconductor chip having a floor plan with a processor core portion having one or more processor cores and a second portion having logic other than a processor core;
at least one second semiconductor chip stacked on a side of the first semiconductor chip, on the second portion, outside of the processor core portion; and
a lid having a first interface surface to seat on the processor core portion and a second interface surface to seat on the at least one second semiconductor chip.