US 12,266,584 B2
Integrated circuit package and method
Hsien-Wei Chen, Hsinchu (TW); Ming-Fa Chen, Taichung (TW); and Sung-Feng Yeh, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 1, 2023, as Appl. No. 18/363,363.
Application 18/363,363 is a division of application No. 17/314,618, filed on May 7, 2021, granted, now 11,848,246.
Claims priority of provisional application 63/165,280, filed on Mar. 24, 2021.
Prior Publication US 2023/0378015 A1, Nov. 23, 2023
Int. Cl. H01L 23/36 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01); H01L 27/06 (2006.01)
CPC H01L 23/36 (2013.01) [H01L 21/56 (2013.01); H01L 23/31 (2013.01); H01L 25/0652 (2013.01); H01L 27/0688 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
an interposer;
a first integrated circuit device attached to the interposer;
a second integrated circuit device attached to the interposer adjacent the first integrated circuit device;
a plurality of heat dissipation dies stacked on the second integrated circuit device, the heat dissipation dies comprising an upper heat dissipation die and a lower heat dissipation die, a width of the upper heat dissipation die being greater than a width of the second integrated circuit device, a width of the lower heat dissipation die being greater than the width of the second integrated circuit device; and
an encapsulant around the heat dissipation dies, the second integrated circuit device, and the first integrated circuit device, a top surface of the encapsulant being coplanar with a top surface of the upper heat dissipation die and a top surface of the first integrated circuit device.