US 12,266,574 B2
Flowable chemical vapor deposition (FCVD) using multi-step anneal treatment and devices thereof
Yun Chen Teng, New Taipei (TW); Chen-Fong Tsai, Hsinchu (TW); Li-Chi Yu, Jhubei (TW); Huicheng Chang, Tainan (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 6, 2022, as Appl. No. 17/738,527.
Claims priority of provisional application 63/230,111, filed on Aug. 6, 2021.
Prior Publication US 2023/0042726 A1, Feb. 9, 2023
Int. Cl. H01L 21/3105 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/823481 (2013.01) [H01L 21/31053 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a flowable dielectric film on a substrate, wherein the flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin;
annealing the flowable dielectric film at a first anneal temperature for an anneal time of at least 5 hours to form a first dielectric film;
annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film;
annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer;
applying a planarization process to the insulating layer such that top surfaces of the first semiconductor fin and the second semiconductor fin and a top surface of the insulating layer are level; and
etching the insulating layer to form shallow trench isolation (STI) regions on the substrate.