US 12,266,573 B2
Transistor isolation regions and methods of forming the same
Yi Chen Ho, Taiching (TW); Yiting Chang, Taoyuan (TW); Chi-Hsun Lin, Hsinchu (TW); and Zheng-Yang Pan, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Sep. 23, 2021, as Appl. No. 17/483,043.
Claims priority of provisional application 63/219,420, filed on Jul. 8, 2021.
Prior Publication US 2023/0008893 A1, Jan. 12, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 27/088 (2006.01)
CPC H01L 21/823481 (2013.01) [H01L 21/0228 (2013.01); H01L 21/76224 (2013.01); H01L 27/0886 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
etching a trench in a substrate;
depositing an insulation material in the trench;
depositing a first ceramic dielectric material on the insulation material and in the trench with a first atomic layer deposition process, the first ceramic dielectric material having a first carbon concentration;
depositing a second ceramic dielectric material on the first ceramic dielectric material and in the trench with a second atomic layer deposition process, the second ceramic dielectric material having a second carbon concentration, the second carbon concentration being greater than the first carbon concentration;
planarizing a top surface of the insulation material with a top surface of the first ceramic dielectric material and a top surface of the second ceramic dielectric material; and
recessing the top surface of the insulation material from the top surface of the first ceramic dielectric material and the top surface of the second ceramic dielectric material.