| CPC H01L 21/823418 (2013.01) [H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |
|
1. A method comprising:
forming isolation regions extending into a semiconductor substrate;
forming a semiconductor fin protruding higher than top surfaces of the isolation regions;
forming a gate stack on the semiconductor fin;
forming a gate spacer on a sidewall of the gate stack;
recessing the semiconductor fin to form a recess;
performing a first epitaxy process to grow a first epitaxy semiconductor layer in the recess, wherein the first epitaxy semiconductor layer has a first dopant concentration, and wherein the first epitaxy semiconductor layer comprises a facet comprising a top end joined to a top corner of the semiconductor fin at a same point, and wherein the top corner is at a joining point where a first outer sidewall of the gate spacer is joined to a second outer sidewall of the semiconductor fin;
performing a second epitaxy process to grow an embedded stressor extending into the recess, wherein the embedded stressor has a second dopant concentration higher than the first dopant concentration, and wherein the embedded stressor comprises:
a top portion higher than a top surface of the semiconductor fin, wherein the top portion has a first sidewall contacting a second sidewall of the gate spacer, and the sidewall has a bottom end level with the top surface of the semiconductor fin; and
a bottom portion lower than the top surface of the semiconductor fin;
after the second epitaxy process, performing a third epitaxy process to grow a semiconductor capping layer over the embedded stressor, wherein the embedded stressor has a higher phosphorus concentration than the semiconductor capping layer; and
forming a silicide region over and contacting an additional top surface of the embedded stressor, wherein the silicide region is spaced apart from the first epitaxy semiconductor layer, with a portion of the embedded stressor being directly underlying the silicide region and spacing the silicide region from the first epitaxy semiconductor layer.
|
|
10. A method comprising:
forming isolation regions extending into a semiconductor substrate, wherein a top portion of a semiconductor strip between the isolation regions forms a semiconductor fin protruding higher than top surfaces of the isolation regions;
forming a gate stack on a top surface and sidewalls of the semiconductor fin;
forming a gate spacer on a sidewall of the gate stack;
epitaxially growing a source/drain region on a side of the semiconductor fin, wherein the epitaxially growing the source/drain region comprises:
epitaxially growing a first semiconductor layer having a first dopant concentration; and
epitaxially growing an embedded stressor over and contacting the first semiconductor layer, wherein the embedded stressor has a second dopant concentration that is a highest dopant concentration in the source/drain region, and wherein the embedded stressor comprises:
an upper portion higher than the top surface of the semiconductor fin, wherein the upper portion of the embedded stressor contacts the gate spacer to form a vertical interface, and wherein a bottom surface of the embedded stressor is slanted and has a topmost end joined to a bottom end of the vertical interface at a same point;
a lower portion lower than the top surface of the semiconductor fin; and
epitaxially growing a semiconductor capping layer over the embedded stressor, wherein the semiconductor capping layer has a lower dopant concentration than the embedded stressor;
forming a source/drain silicide region over and physically contacting a top surface of the embedded stressor; and
forming a contact plug over and contacting the source/drain silicide region, wherein the source/drain silicide region and the contact plug collectively penetrate through the semiconductor capping layer.
|
|
18. A method comprising:
forming a gate stack on a semiconductor fin, wherein the semiconductor fin protrudes higher than dielectric isolation regions on opposite sides of the semiconductor fin;
forming a source/drain region extending into the semiconductor fin, wherein the forming the source/drain region comprises growing an embedded stressor, and the embedded stressor comprises:
a V-shaped bottom surface, wherein a top end of the V-shaped bottom surface is at a same level as a top surface of the semiconductor fin, wherein the V-shaped bottom surface has a lowest point in middle between the gate stack and an additional gate stack neighboring the gate stack, and wherein the V-shaped bottom surface has increased heights all the way from the lowest point to a topmost point of the V-shaped bottom surface;
a V-shaped top surface, wherein a first portion of the V-shaped top surface is higher than the top surface of the semiconductor fin, and a second portion of the V-shaped top surface is lower than the top surface of the semiconductor fin; and
forming a semiconductor capping layer over and contacting the embedded stressor that has a highest dopant concentration, wherein the semiconductor capping layer has a lower dopant concentration than the embedded stressor, and wherein the embedded stressor has the highest dopant concentration in the source/drain region;
forming a source/drain silicide region contacting an additional top surface of the embedded stressor; and
forming a contact plug over and contacting the source/drain silicide region, wherein a sidewall of the contact plug is in contact with an addition sidewall of the semiconductor capping layer.
|